The present disclosure relates generally to integrated circuits, such as field programmable gate arrays (FPGAs). More particularly, the present disclosure relates to host program guided memory allocation on integrated circuits (e.g., an FPGA).
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Integrated circuits (ICs) take a variety of forms. For instance, field programmable gate arrays (FPGAs) are integrated circuits that are intended as relatively general-purpose devices. FPGAs may include logic that may be programmed (e.g., configured) after manufacturing to provide any desired functionality that the FPGA is designed to support. Thus, FPGAs contain programmable logic, or logic blocks, that may be configured to perform a variety of functions on the FPGAs, according to a designer's design. Additionally, FPGAs may include input/output (I/O) logic, as well as high-speed communication circuitry. For instance, the high-speed communication circuitry may support various communication protocols and may include high-speed transceiver channels through which the FPGA may transmit serial data to and/or receive serial data from circuitry that is external to the FPGA. For example, certain programming languages, such as OpenCL, may enable hosting of programmable logic off the IC, enabling functionalities of the IC to be controlled, or at least impacted, by an external host.
In ICs such as FPGAs, the programmable logic is typically configured using low level programming languages such as VHDL or Verilog. Unfortunately, these low level programming languages may provide a low level of abstraction and, thus, may provide a development barrier for programmable logic designers. Higher level programming languages, such as OpenCL have become useful for enabling more ease in programmable logic design. The higher level programs are used to generate code corresponding to the low level programming languages. Kernels may be useful to bridge the low level programming languages into executable instructions that may be performed by the integrated circuits. Accordingly, OpenCL programs typically utilize at least a single hardware implementation for each kernel in the OpenCL program. Unfortunately, as these programs become more complex and/or sophisticated, the performance of the implementation on the integrated circuit may be negatively impacted. For example, global memory bandwidth may oftentimes be a limiting factor in the performance of an OpenCL application.
Boards that implement OpenCL hardware platforms often use multiple dual in-line memory modules (DIMMs) or banks of memories to implement high-bandwidth external memory systems. The bandwidth performance is directly dependent on a kernel's specific memory access pattern and the organization of data across the banks. Unfortunately, in traditional systems, the programmable logic design has very little control over the memory access pattern or the organization of the data across the banks. Accordingly, a system that enables enhanced guidance of memory allocation by a programmable logic design is desired.